AES in CDL Part 6 - CTR mode of Operation

This post is the sixth part in my AES in CDL series. In this post, I create a module to implement the Counter mode of operation.

AES in CDL Part 5 - Running on Hardware

This post is the fifth part in my AES in CDL series. In this post, I correct some mistakes I made in my previous version, synthesized the module and ran it on the Zynq7000.

AXI Interface Part 2 - Proof-of-Concept Implementation

In this post I created a simple CDL module to test a memory-like interface for moving data between the programmable logic and processing system of the Zynq7000

AXI Interface Part 1 - Memory-like AXI Interface

In this post I cover creating a simple memory-like AXI-4 interface between the Zynq7000 programmable logic and DDR. I intend to expand on this interface to facilitate a data path for my CDL encryption algorithm implementations.

AES in CDL Part 4 - Encryption in Verilog

This post is the fourth in my series on the AES crypto algorithm and my implementation of it in CDL. In this post, I described my implementation of the encryption portion of the algorithm in Verilog.